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W5280 ADPCM VOICE SYNTHESIZER (ROM-less PowerSpeech)
GENERAL DESCRIPTION
The W5280 is a CMOS IC that is used solely for the purpose of demonstrating W528X series PowerSpeech products. The W5280 employs the same JUMP-GO architecture as most of Winbond's other speech synthesizers. Unlike standard products, however, the W5280 does not include a built-in memory, because the chip is designed to serve only as a demonstration chip for the W528X series PowerSpeech ICs. The W5280 has an ADPCM synthesizer, an 8-bit D/A converter, and all other necessary control and timing logic, but it must be operated with an external memory device (OTP). The W5280's LOAD and JUMP commands and four programmable registers provide powerful userprogrammable functions that make this chip suitable for an extremely wide range of speech IC applications.
FEATURES
* * * * * * * * * * *
Serves as demo chip for W528X series products (no built-in ROM) Oscillator frequency adjustable by external resistor Wide operating voltage range: 2.4 to 5.0 volts 4-bit ADPCM synthesizer method and built-in 8-bit D/A converter Provides 4 direct trigger inputs that can easily be extended to 8 or 12 matrix trigger inputs Two trigger input debounce time settings (20 to 40 mS or 160 to 320 S) through register control Provides up to 2 LEDs and 3 STOP outputs Every LED pin drives up to 3 LEDs simultaneously LED flash frequency: 3 Hz AUD output current: 5 mA Flexible functions programmable through the following: - LD (load), JP (jump) commands - Four registers: R0, EN, STOP, and MODE - Conditional instructions - Speech equation - END instruction - Global repeat (GR) setting - Output frequency and LED flash type setting
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Programmable power-on initialization (POI) (can be interrupted by trigger inputs) POI delay time of 160 mS to maintain stable voltage when chip is powered on
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Publication Release Date: March 1996 Revision A2
W5280
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Can be programmed for the following functions: - Interrupt or non-interrupt for rising or falling edge of each trigger pin (this feature determines retriggerable, non-retriggerable, overwrite, and non-overwrite features of each trigger pin) - Four playing modes: One Shot (OS) Level Hold (LH) Single-cycle level hold (S_LH) Complete-cycle level hold (C_LH) - Stop output signal setting - Serial, direct, or random trigger mode setting
* * * *
Four frequency options (4/4.8/6/8 KHz) and LED On/Off control can be set independently in each GO instruction of speech equation Independent control of LED 1 and LED 2 Total of 256 voice group entries available for programming Provides the following mask options: - LED flash type: synchronous/alternate - LED 1 section-controlled: Yes/No - LED 2 section-controlled/STPC-controlled - LED volume-controlled: No/Yes
PIN CONFIGURATION
TG1 TG2 TG3 TG4/LED2/STPC LED1 STPB STPA NC SPK VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
WRP DATA RDP NC NC NC NC DISOTP OSC V DD
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W5280
PIN DESCRIPTION
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME TG1 TG2 TG3 TG4/LED2/STPC LED1 STPB STPA NC SPK VSS VDD OSC DISOTP NC NC NC NC RDP DATA WRP I/O I I I I/O O O O O I I O I/O O Trigger Input 1 Trigger Input 2 Trigger Input 3 Trigger Input 4 or LED 2 or Stop Signal C LED 1 Stop Signal B Stop Signal A Not Connected Current Output for Speaker Negative Power Supply Positive Power Supply Oscillation Frequency Control Connects to ground to disable OTP and speech interface; data can then be burned into OTP directly Not connected Not connected Not connected Not connected Read pulse clock output for serial interface Bidirectional data pin for serial interface Write pulse clock output for serial interface FUNCTION
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Publication Release Date: March 1996 Revision A2
W5280
BLOCK DIAGRAM
OSC
TIMING GENERATOR
DATA EXTERNAL
TG1 TG2 TG3 TG4/LED2/STPC LED1 DISOTP STPA STPB CONTROLLER
INTERFACE CIRCUIT
WRP RDP
ADPCM SYNTHESIZER
SHIFT REGISTER
D/A CONVERTER
VDD
VSS
SPK
FUNCTIONAL DESCRIPTION
The W5280 provides up to four direct trigger pins (which can be extended to eight or twelve matrix trigger inputs), up to three stop signal output pins, an LED section control, and powerful programmable features. The JUMP and LOAD commands and four programmable registers can be used to program the desired playing mode, stop output signal form, LED flash type, and trigger pin interrupt modes. The chip's programmable features can also be used to develop new, customized functions for a wide variety of innovative applications.
A. Instruction Set Description
This section describes three types of instructions:
* * *
Unconditional instructions, which are executed immediately after they are issued. Conditional instructions, which are executed only when the conditions specified in the instructions are satisfied. END instruction, which is used to stop all device activity.
Instructions are programmed by writing LOAD and JUMP commands into the R0, EN, STOP, and MODE registers. Unconditional Instructions: -4-
W5280
1. LOAD (LD) Command: LD R0, value: This instruction is used to load a voice-group entry value into register R0. The voicegroup entry value may range from 0 to 255. The initial value of the R0 register is "00000000." LD EN, operand: This instruction is used to define the trigger interrupt settings by loading the operand message into register EN. The initial value of the EN register is "11111111." a. The operand is an 8-bit value that can be entered in decimal (default) or hexadecimal (with "0x" as a prefix). b. EN is an 8-bit register that is used to enable/disable the rising/falling edge of each of the four trigger inputs. The 8 bits correspond to the rising/falling edges of the triggers as shown below: Bit: TG: 7 4R 6 3R 5 2R 4 1R 3 4F 2 3F 1 2F 0 1F
where "nR/F" represents the rising/falling edge of the n-th trigger pin. c. When any one of the eight bits is set to "1" (default), the corresponding trigger will interrupt the current state at the edge indicated. When the bits are set to "0," the triggers will be disabled. d. The voice group entry addresses correspond to the interrupt vectors as follows: TG: Group: EXAMPLE: The instruction "LD EN, 0x41" is programmed. EXPLANATION: a. "41" is a hexadecimal value equal to the binary value "0100 0001." b. These 8 bits of data represent the following trigger interrupt settings: TG: Bit RESULT: a. When the rising edge of TG3 (3R) is activated, the EN register will cause TG3 to interrupt the current playing state and jump immediately to voice group 6, the voice group that corresponds to 3R. b. When the falling edge of TG1 (1F) goes active, the EN register will cause TG1 to interrupt the current playing state and jump immediately to voice group 0, the voice group that corresponds to 1F. 4R 0 3R 1 2R 0 1R 0 4F 0 3F 0 2F 0 1F 1 4R 7 3R 6 2R 5 1R 4 4F 3 3F 2 2F 1 1F 0
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Publication Release Date: March 1996 Revision A2
W5280
c. No action will be taken when the other trigger pins are pressed, because the corresponding bits are set to "0." LD STOP, operand: This instruction loads the operand message into the STOP register to set the output levels of the stop signals. The initial value of the STOP register is "XXXXX111." a. This register is used to program the output levels of the three STOP signals, STPA, STPB, and STPC. Only three of the bits in the register are used, as shown below (an "X" indicates "Don't care"): Bit: STOP: 7 X 6 X 5 X 4 X 3 X 2 STPC 1 STPB 0 STPA
b. When a particular STOP bit is set to "1," The corresponding stop signal will be a high output; when a bit is set to "0," the corresponding stop signal will be a low output. EXAMPLE: The instruction "LD STOP, 0x43" is programmed. EXPLANATION: a. "43" is a hexadecimal value equal to a binary value of "0100 0011." b. These 8 bits of data represent the following settings: Bit: STOP: RESULT: a. The STPA and STPB outputs will be high outputs. b. The STPC signal will be a low output. c. The sixth bit "1" is a "Don't Care" bit and so has no effect on the stop signal output settings. LD MODE, operand: This instruction is used to select among various operating modes. It loads an operand message into the MODE register to select one mode from each of four pairs of modes, which correspond to bits 4 through 7 of the register (bits 0 to 3 are "Don't Care" bits). The four pairs of modes and the corresponding bits are as follows: Bit: MODE: 7 Flash/DC 6 LED2/STPC 5 TG4/LED2_STPC 4 20 mS/160 S 3 X 2 X 1 X 0 X 0 X 1 X 0 X 0 X 0 X 0 STPC 1 STPB 1 STPA
A "1" for one of these bits selects the first of the pair of modes indicated; a "0" selects the second of the pair. The initial value of the mode register is "1111XXXX."
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W5280
EXAMPLE 1: The four bits are programmed as "1111," so that the eight bits of the register are as follows (an "X" indicates a "Don't Care" bit): Bit: MODE: RESULT: The mode settings are as follows: a. Pin 4 (TG4/LED2_STPC) is configured as a trigger pin (TG4), and the LED2/STPC option will be ignored. b. The LED is set as a flash type, with a flash frequency of 3 Hz. c. The debounce time of the trigger inputs is set to 20 mS. EXAMPLE 2: The four bits are programmed as "0000," so that the eight bits of the register are as follows (an "X" indicates a "Don't Care" bit): Bit: MODE: RESULT: The mode settings are as follows: a. Pin 4 (TG4/LED2_STPC) is configured as either the LED2 or STPC output (determined by bit 6, LED2/STPC; see next item). b. Pin 4 is configured as the STPC output pin. c. LED will be lit constantly during operation. d. The debounce time of the trigger inputs is set as 160 S. 2. JUMP (JP) Command: JP value: Instructs device to jump directly to the voice group corresponding to the value indicated. The voice group value may range from 0 to 127 (direct jump). JP R0: Instructs device to jump to whatever voice group is indicated by the value currently stored in register R0, from 0 to 255 (indirect jump). Conditional Instructions: Conditional instructions are executed only when the conditions specified in the instructions hold. The conditional instructions are listed below. An explanation of the notation used in the instructions follows.
(Note: There are no conditional instructions for LD MODE.)
1 Flash/DC
1 LED2/STPC
1 TG4/LED2_STPC
1 20 mS/160 S
X X
X X
X X
X X
0 Flash/DC
0 LED2/STPC
0 TG4/LED2_STPC
0 20 mS/160 S
X X
X X
X X
X X
LD R0, VALUE @LAST: VALUE can be set from 0 to 255.
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Publication Release Date: March 1996 Revision A2
W5280
LD R0, VALUE @TGn_STATUS: VALUE can be set from 0 to 255. LD EN, OPERAND @LAST: EN-4R, 3R, 2R, 1R, 4F, 3F, 2F, 1F. LD STOP, OPERAND @LAST: STOP-X, X, X, X, X, STC, STB, STA. JP VALUE @LAST: VALUE can be set from 0 to 127 JP R0 @LAST JP VALUE @TGn_STATUS: VALUE can be set from 0 to 127 JP R0 @TGn_STATUS EXPLANATION: @LAST: At last time of global repeat. @TGn_STATUS: When the status of the trigger specified (TGn) is in the condition specified, where the possible triggers and conditions are the following: TG1_HIGH TG1_LOW TG2_HIGH TG2_LOW TG3_HIGH TG3_LOW TG4_HIGH TG4_LOW End Instruction: END: This command instructs the chip to cease all activity immediately.
B. Program Structure Features and Execution Rules
1. There are eight hardware group entry points and 248 software group entry points, as follows: Group 8 H/W entries: TG1F: TG2F: TG3F: TG4F: TG1R: TG2R: TG3R: 0 1 2 3 4 5 6
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W5280
Continued
TG4R: 248 S/W entries:
7 8 9 . . . 32 33 . . . 254 255
POI:
2. Execution begins from group entry and is terminated by END instruction. 3. A H/W trigger interrupt stops the group currently being executed immediately and begins a new group.
C. Mask Options
There are several mask options for the W5280; the mask options are used to select features that can be demonstrated when the chip is used with an OTP. (The LED flash frequency (3 Hz fixed) and the AUD output current (5 mA fixed) cannot be adjusted.) The mask options that can be demonstrated are the following: LED flash type (synchronous/alternate) LED volume-controlled: No/Yes LED1 section-controlled: Yes/No LED2: section-controlled/STPC-controlled
D. Speech Equation Description
The format of the speech equations for the W5280 is as follows: GR = N H4+m1*SOUND1_FL+m2*SOUND2_FL+[1FFFF]+... +T4 END where GR = N defines the number of global repeats (from 1 to 16); m1 and m2 define the number of local repeats (from 1 to 7); SOUND1 and SOUND2 are the *.WAM files of ADPCM converted voice data; _FL is the section control setting, for which the parameters F and L are as follows: Publication Release Date: March 1996 Revision A2
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W5280
F: Voice output frequency setting: F Frequency (KHz) L: LED output setting: L LED state 0 Off 1 On 0 4 1 4.8 2 6 3 8
[1FFFF] is a period of silence of length 1FFFF; H4, T4: Represent head and tail ADPCM files, respectively.
E. Programmable Power-on Initialization
Whenever the W5280 is powered on, the program contained in the 32th voice group will be executed after the power-on delay (about 160 mS), so the user can write a program into this group to set the power-on initial state. If the user does not wish to execute a program at power-on, an "END" instruction should be entered in group 32. The W5280 power-on initialization process can be interrupted by trigger inputs.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Power Supply Input Voltage Storage Temp. Operating Temp. SYMBOL VDD-VSS VIN TSTG TOPR CONDITIONS All Inputs RATED VALUE -0.3 to +7.0 VSS -0.3 to VDD +0.3 -55 to +150 0 to +70 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC CHARACTERISTICS
(TA = 25 C, VSS = 0 V)
PARAMETER
SYM.
CONDITIONS MIN.
LIMITS TYP. 3 LIMITS MIN. TYP. MAX. MAX. 5.0 0.3 VDD VDD
UNIT
Operating Voltage Input Voltage
DC Characteristics, continued
VDD VIL VIH
All Input Pins
2.4 VSS -0.3 0.7 VDD
V V
PARAMETER
SYM.
CONDITIONS
UNIT
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W5280
Standby Current IDD1 IDD2 Operating Current IOP1 IOP2 Input Current for TG1-TG4 SPK (D/A Full Scale) Output Current of STPC LED1 Output Current LED2 STPA STPB Oscillation Freq. Oscillation Freq. Deviation by Voltage Drop Input Debounce Time
Note: ROSC = Typ. = 1.2 M.
VDD = 3 V, No Playing VDD = 5 V, No Playing VDD = 3 V, No Load VDD = 5 V, No Load VDD = 3 V, VIN = 0 V VDD = 4.5 V, RL = 100 VDD = 3 V, VOUT = 0.4 V VDD = 3 V, VOUT = 2.7 V VDD = 3 V, VOUT = 1 V VDD = 4.5 V, VOUT = 1 V VDD = 3 V, VOUT = 0.4 V VDD = 3 V, VOUT = 2.7 V VDD = 3 V, ROSC = Typ. VDD = 4.5 V, ROSC = Typ. F(3 V) - F(2.4 V) F(3 V) FOSC = 3 MHz
-4.0 1 -0.5 10 15 1 -1 2.7 2.7 0 20 160
-5.0 3 -3 3 3 4 30 240
0.2 0.4 400 800 6 -6.0 3.3 3.3 7.5 40 320
A A A mA mA
IIN IO1 IOL IOH IO IoL IOH FOSC FOSC FOSC TDEB1 TDEB2
mA
MHz
% mS S
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Publication Release Date: March 1996 Revision A2
W5280
TYPICAL APPLICATION CIRCUIT
VDD
TG1 TG2 TG3 TG4/LED2/STPC R 39/100 Ohm Speaker 8 ohm 1/4 watt 8050D Cs Rs LED1 STPB STPA NC SPK VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17
WRP DATA RDP NC NC
S1/CE1 S2/CE2 VSS WRP 1M Ohm
S0/CE0 VDD
OTP
RDP DATA
W5280
16 15 14 13 12 11
NC NC DISOTP OSC VDD Rosc GND to burn OTP
Notes: 1. In principle, the playing speed determined by ROSC should correspond to the sampling rate during the coding phase. The playing speed may be adjusted by varying ROSC, however. 2. Rs is an optional current-dividing resistor. If Rs is added, the resistance should be between 470 and 750 . 3. R is used to limit the current on the LED. Case 1: VDD = 3 V, R = 39 for 1/2/3 LEDs. Case 2: VDD = 4.5 V, R = 39 for 2/3 LEDs and R = 100 for 1 LED. 4. Cs is optional. 5. The DC current gain of transistor 8050 ranges from 120 to 200. 6. All unused trigger pins can be left open because of their internal pull-high resistance. 7. No warranty for production.
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W5280
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27516023 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: March 1996 Revision A2

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